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LXT336
Quad T1/E1 Receiver
Datasheet
The LXT336 quad receiver is a fully-integrated, quadruple-PCM receiver for both T1 (1.544 Mbps) and E1 (2.048 Mbps) applications. It incorporates four independent receivers in a single 64-pin QFP package. The LXT336 features a differential receiver architecture with high noise interference margin. It uses peak detection with a variable threshold for reliable recovery of data as low as 500 mV and up to 12 dB of cable attenuation. The fully digital clock recovery system uses a low frequency master clock of 2.048 MHz or 1.544 MHz as its reference. In addition, each LXT336 receiver incorporates a Loss of Signal (LOS) detection circuit. The LOS detector is compliant with both ITU-T G.775 and ANSI T1.231 standards. The LXT336 ports can be independently configured for either unipolar or bipolar output modes. HDB3 and AMI decoding mechanisms are available in unipolar mode.
Applications
s s
Test Equipment DSX-1 and E1 Line Monitoring
s
High density T1/E1 line cards
Product Features
s s s s s
Fully integrated quad, receiver for E1 2.048 Mbps or T1 1.544 Mbps operation Single rail supply voltage of 5 V (typical) Low power consumption: 250 mW for E1; 200 mW for T1 (typical) High-performance receivers recover data with up to 12 dB cable attenuation On-chip clock recovery function complies with ITU G.823 and Bellcore GR-499CORE
s s s s s s
Low frequency 1.544 or 2.048 MHz reference clock Programmable unipolar and bipolar PCM interface On-chip AMI and HDB3 decoders Loss of Signal processors conform to ITU G.775 and ANSI T1.231 recommendations Small-footprint 64-pin QFP Optional RZ Data recovery mode
As of January 15, 2001, this document replaces the Level One document LXT336 -- Quad T1/E1 Receiver.
Order Number: 249046-001 January 2001
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT336 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners.
Datasheet
Quad T1/E1 Receiver -- LXT336
Contents
1.0 2.0 Pin Assignments & Signal Descriptions\ ......................................................... 6 Functional Description...........................................................................................10
2.1 Receiver Description ...........................................................................................10 2.1.1 Loss Of Signal Detector .........................................................................10 2.1.1.1 E1 LOS Detection......................................................................10 2.1.1.2 T1 LOS Detection......................................................................11 2.1.1.3 Data Recovery Mode LOS Detection ........................................11 2.1.1.4 In-Service Code Violation Monitoring ........................................11 Monitoring Applications .......................................................................................12 3.1.1 Receive Line Interface Applications .......................................................13
3.0
Application Information.........................................................................................12
3.1
4.0 5.0
Test Specifications ..................................................................................................16 Mechanical Specifications....................................................................................22
Figures
1 2 3 4 5 6 7 8 LXT336 Block Diagram ......................................................................................... 5 LXT336 Pin Assignments and Package Markings ................................................ 6 Typical Monitoring Application.............................................................................13 Typical Receive Line Interface Application..........................................................14 LXT336 Receive Timing Diagram .......................................................................19 E1 Jitter Tolerance--G.823.................................................................................20 T1 Jitter Tolerance--GR-499-CORE Category II ................................................21 Package Specifications .......................................................................................22
Tables
1 2 3 4 5 6 7 8 9 LXT336 Pin Descriptions....................................................................................... 7 Transformer Specifications..................................................................................15 Absolute Maximum Ratings.................................................................................16 Recommended Operating Conditions .................................................................16 DC Characteristics (Over Recommended Range) ..............................................16 E1 Receive Characteristics (Over Recommended Range) .................................17 T1 Receive Characteristics (Over Recommended Range) .................................18 Timing Characteristics (Over Recommended Range).........................................19 Relevant Recommendations ...............................................................................21
Datasheet
3
LXT336 -- Quad T1/E1 Receiver
Revision History
Revision Date Description
4
Datasheet
Quad T1/E1 Receiver -- LXT336
Figure 1. LXT336 Block Diagram
MODE UBS LOS RPOS/ RDATA RNEG/ BPV RCLK MCLK
LOS Detector AMI / HDB3 Unipolar Decoder Data Recovery Clock Recovery
Data Slicers Peak Dectector
RTIP RRING
Port 0 Port 1 Port 2 Port 3
Datasheet
5
LXT336 -- Quad T1/E1 Receiver
1.0
Pin Assignments & Signal Descriptions\
Figure 2. LXT336 Pin Assignments and Package Markings
Package Topside Markings Marking Part # Rev # Lot # FPO # Unique identifier for this product family. Identifies the particular silicon "stepping" -- refer to the specification update for additional stepping information. Identifies the batch. Identifies the Finish Process Order. Definition
6
GND MODE RRING0 RTIP0 LOS0 RRING1 RTIP1 LOS1 RRING2 RTIP2 LOS2 RRING3 RTIP3 LOS3 GND CLKE
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MCLK CLKI0 GND UBS0 CLKI1 GND UBS1 GND NC GND VCC NC NC GND VCC NC
1 2 3 4 5 6 7 8 9 Part # 10 LOT # 11 FPO # 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RCLK0 RPOS0 / RDATA0 RNEG0 /BPV0 RCLK1 RPOS1 / RDATA1 RNEG1 / BPV1 NC NC NC NC RCLK2 RPOS2 / RDATA2 RNEG2 / BPV2 RCLK3 RPOS3 / RDATA3 RNEG3 / BPV3
LXT336QE XX XXXXXX XXXXXXXX
Rev #
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
NC CLKI3 GND UBS3 CLKI2 GND UBS2 VCC NC GND VCC NC NC GND VCC NC
Datasheet
Quad T1/E1 Receiver -- LXT336
Table 1.
Pin #
LXT336 Pin Descriptions
Sym I/O1 Description Master Clock Input. An independent and free-running 2.048 or 1.544 MHz clock input generates the internal reference clocks for all Receivers. On Loss of Signal (LOS), the LXT336 derives RCLKx from this master clock. With MCLK asserted High, the LXT336 disables the PLL clock recovery circuits. The Receiver then feeds RPOSx and RNEGx to an internal XOR gate that performs logically exclusive ORs for both data signals and connects this output to RCLKx for external clock recovery. In this mode, the LXT336 operates as a data recovery circuit. With MCLK asserted Low, the LXT336 powers down its clock and data recovery circuits and switches the output pins RCLKx, RPOSx and RNEGx to tri-state mode. MCLK Operating Mode Clocked Data/Clock Recovery L Power Down H Data Recovery Clock Input - Port 0. All CLKIx pins are identical. Connect to MCLK for unipolar operation mode (single rail plus clock). For bipolar operation mode (dual rail plus clock), CLK0 should be connected to ground. Ground. Unipolar-Bipolar Select Input-Port 0. All UBSx pins are identical. If this pin is asserted High for more than 16 CLKI cycles, the LXT336 switches to unipolar mode. HDB3 or AMI decoder mode is selected by the MODE pin.
1
MCLK
DI
2 3
CLKI0 GND
DI S
4
UBS0
DI
The device is set to bipolar mode when this pin is asserted Low. UBSx Operating Mode L Bipolar Mode H Unipolar Mode Clock Input - Port 1. See CLKI0, pin 2. Ground. Unipolar-Bipolar Select Input-Port 1. See UBS0, pin 4. Ground. Not Connected. Must be left open. Ground. Positive Supply. +5 VDC power supply. Not Connected. Must be left open. Not Connected. Must be left open. Ground. Positive Supply. +5 VDC power supply. Not Connected. Must be left open. Ground.
5 6 7 8 9 10 11 12 13 14 15 16 17
CLKI1 GND UBS1 GND NC GND VCC NC NC GND VCC NC GND
DI S DI S S S S S S
1. Entries in I/O column are: DI = digital input; DO = digital output; DI/O = digital input/output; AI = analog input; AO = analog output; S = supply. Note: Do not leave digital inputs floating, with the exception of not connected (NC) pins.
Datasheet
7
LXT336 -- Quad T1/E1 Receiver
Table 1.
Pin #
LXT336 Pin Descriptions (Continued)
Sym I/O1 Description Mode Select Input. In unipolar mode, if this pin is pulled Low, all transceivers operate in E1 mode using AMI decoding. With this pin pulled High, all transceivers enter E1 mode using HDB3 decoding. With this pin set to 2.5V, the LXT336 enters T1 mode with AMI decoding. MODE Operating Mode L E1 Mode with AMI Decoding H E1 Mode with HDB3 Decoding 2.5V T1 Mode with AMI Decoding The 2.5V reference is obtained with a resistive divider consisting of two 10 K resistors across VCC and GND.
18
MODE
DI
19 20 21 22 23 24 25 26 27 28 29 30 31
RRING0 RTIP0 LOS0 RRING1 RTIP1 LOS1 RRING2 RTIP2 LOS2 RRING3 RTIP3 LOS3 GND
AI AI DO AI AI DO AI AI DO AI AI DO S
Receive Ring Input-Port 0/Receive TIP Input-Port 0. These pins are the inputs of the fully differential line receiver. Loss of Signal Output-Port 0. All LOSx pins are identical. This output is High when a valid loss of signal condition is detected. See page 10 for more information. In data recovery mode, LOSx is a pure analog energy detector. Receive Ring Input-Port 1/Receive TIP Input-Port 1. See RRING0, pin 19; RTIP0, pin 20. Loss of Signal Output-Port 1. See LOS0, pin 21. Receive Ring Input-Port 2/Receive TIP Input-Port 2. See RRING0, pin 19; RTIP0, pin 20. Loss of Signal Output-Port 2. See LOS0, pin 21. Receive Ring Input-Port 3/Receive TIP Input-Port 3. See RRING0, pin 19; RTIP0, pin 20. Loss of Signal Output-Port 3. See LOS0, pin 21. Ground. Clock Edge Select Input. CLKE Result L RPOS, RNEG valid on falling edge of RCLK H RPOS, RNEG valid on rising edge of RCLK Not Connected. Must be left open. Positive Supply. +5 VDC power supply. Ground. Not Connected. Must be left open. Not Connected. Must be left open. Positive Supply. +5 VDC power supply. Ground. Not Connected. Must be left open. Positive Supply. +5 VDC power supply Unipolar-Bipolar Select Input-Port 2. See UBS0, pin 4. Ground. Clock Input - Port 2. See CLKI0, pin 2. Unipolar-Bipolar Select Input-Port 3. See UBS0, pin 4.
32
CLKE
DI
33 34 35 36 37 38 39 40 41 42 43 44 45
NC VCC GND NC NC VCC GND NC VCC UBS2 GND CLKI2 UBS3
S S S S S DI S DI DI
1. Entries in I/O column are: DI = digital input; DO = digital output; DI/O = digital input/output; AI = analog input; AO = analog output; S = supply. Note: Do not leave digital inputs floating, with the exception of not connected (NC) pins.
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Datasheet
Quad T1/E1 Receiver -- LXT336
Table 1.
Pin # 46 47 48
LXT336 Pin Descriptions (Continued)
Sym GND CLKI3 NC I/O1 S DI Ground. Clock Input - Port 3. See CLKI0, pin 2. Not Connected. Must be left open. Receive Negative Data/Bipolar Violation Indication Output-Port 3. All RNEGx/BPVx pins are identical. In bipolar mode these pins act as active High bipolar non-return-to-zero (NRZ) receive signal outputs. A High signal on RNEGx corresponds to receipt of a negative pulse on RTIPx/RRINGx. A High signal on RPOSx corresponds to receipt of a positive pulse on RTIPx/RRINGx. Both signals are valid on the same edge of RCLKx, as determined by the CLKE pin. In unipolar mode, the LXT336 asserts the BPVx pin High any time it senses an In-Service Line Code violation. In data recovery mode, this pin is an active Low RZ output. See RPOS3/RDATA3, pin 50; and Functional Description. Receive Positive Data/Receive Data Output-Port 3. A High signal on RPOSx corresponds to receipt of a positive pulse on RTIPx/RRINGx. Description
49
RNEG3/ BPV3
DO
50
RPOS3/ RDATA3
DO
In unipolar mode, the LXT336 asserts RDATAx High when a mark has been received. This signal is valid on the edge of RCLKx as determined by the CLKE pin. RDATAx is an NRZ receive data output. In Data Recovery mode, this pin is an active Low RZ output. See RNEG3/BPV3, pin 49. Receive Clock Output-Port 3. All RCLKx pins are identical. This pin provides the recovered clock from the signal received at RTIPx and RRINGx. In loss of signal conditions the LXT336 connects MCLK to this pin through internal circuitry. Asserting the MCLK pin High disables the clock recovery circuit and internally connects RPOSx and RNEGx to an XOR that is fed to the RCLKx output for external clock recovery applications. Receive Negative Data/Violation Indication Output-Port 2. See RNEG3/BPV3, pin 49; RPOS3/RDATA3, pin 50. Receive Positive Data/Receive Data Output-Port 2. See RPOS3/RDATA3, pin 50; RNEG3/BPV3, pin 49. In Data Recovery Mode, this signal is active Low. Receive Clock Output-Port 2. See RCLK3, pin 51. Not connected. Must be left open. Not connected. Must be left open. Not connected. Must be left open. Not connected. Must be left open. Receive Negative Data/Bipolar Violation Indication Output-Port 1. See RNEG3/ BPV3, pin 49; RPOS3/RDATA3, pin 50. Receive Positive Data/Receive Data Output-Port 1. See RPOS3/RDATA3, pin 50; RNEG3/BPV3, pin 49. Receive Clock Output-Port 1. See RCLK3, pin 51. Receive Negative Data/Bipolar Violation Indication Output-Port 0. See RNEG3/ BPV3, pin 49; RPOS3/RDATA3, pin 50. Receive Positive Data/Receive Data Output-Port 0. See RPOS3/RDATA3, pin 50; RNEG3/BPV3, pin 49. Receive Clock Output-Port 0. See RCLK3, pin 51.
51
RCLK3
DO
52
RNEG2/BPV2 RPOS2/ RDATA2 RCLK2 NC NC NC NC RNEG1/BPV1 RPOS1/ RDATA1 RCLK1 RNEG0/BPV0 RPOS0/ RDATA0 RCLK0
DO
53 54 55 56 57 58 59 60 61 62 63 64
DO DO DO DO DO DO DO DO
1. Entries in I/O column are: DI = digital input; DO = digital output; DI/O = digital input/output; AI = analog input; AO = analog output; S = supply. Note: Do not leave digital inputs floating, with the exception of not connected (NC) pins.
Datasheet
9
LXT336 -- Quad T1/E1 Receiver
2.0
Functional Description
The LXT336 quad receiver is a fully-integrated, PCM receiver for both 1.544 Mbps (DSX-1) and 2.048 Mbps (E1) applications. The MCLK frequency and the MODE pin input level set the mode of operation. The LXT336 is a low-power CMOS device operating from a single +5 V power supply. Refer to the LXT336 block diagram on page 1. Each receiver interfaces with back-end processors through bipolar or unipolar data I/O channels and allows control by hardwired pins for stand-alone operation.
2.1
Receiver Description
The four receivers in the LXT336 are identical. The following paragraphs describe the operation of a single receiver. The LXT336 receives the input signal at RTIP/RRING via a 1:1 or 1:2 coupling transformer. Data slicers and a peak detector process the received signal. The peak detector samples the received signal and determines its maximum value. A data-rate dependent percentage of peak value goes to the data slicers as a threshold level to ensure an optimum signal-to-noise ratio. The receiver accurately recovers signals with up to -12 dB of cable loss. The minimum receiver sensitivity signal level is approximately 500 mV peak to peak. Regardless of the received signal level, the LXT336 holds its peak detectors above a minimum level (0.225 V) to provide immunity from impulse noise. After the data slicers process the received signal, it is fed to the data and timing recovery section, and to the receive monitor. The data and timing recovery circuits provide an input jitter tolerance significantly better than required by ITU-T G.823 and GR-499-CORE Category II. Refer to the Test Specifications section for details. The recovered clock is output at RCLK in both bipolar and unipolar modes. In bipolar mode, recovered data is active High and output at RPOS and RNEG; in unipolar mode recovered data is active High and output at RDATA. If CLKE is Low, RPOS and RNEG outputs are valid on the falling edge of RCLK. If CLKE is High, RPOS and RNEG outputs are valid on the rising edge of RCLK. Asserting MCLK High disables the clock recovery function and switches all receivers to data recovery mode. In data recovery mode, the RPOS/RNEG outputs are active Low, return-to-zero (RZ) outputs. Asserting MCLK Low powers all receivers down and holds RPOS/RNEG and RCLK in a high impedance state.
2.1.1
2.1.1.1
Loss Of Signal Detector
E1 LOS Detection
During E1 operation, the ITU G.775 detection criterion is employed. The Loss of Signal (LOS) detector uses a combination analog and digital detection scheme and complies with the ITU G.775 recommendation.
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Datasheet
Quad T1/E1 Receiver -- LXT336
The receiver monitor loads a digital counter at the RCLK frequency. The monitor increments the counter with each received 0 (space), and resets it to 0 with each received 1 (mark). Any signal 21 dB below the nominal 0 dB signal for 32 consecutive pulse intervals generates a LOS condition. The LXT336 sets the LOS flag, and replaces the recovered clock with MCLK at the RCLK output in a smooth transition. (Normal operation requires MCLK.) LOS is cleared again when the signal level rises above 21 dB (typical) below the minimum 0 dB level and the average 1s density reaches 12.5% (i.e. four marks in a 32-bit window). Another smooth transition replaces MCLK with the recovered clock at RCLK. During LOS conditions, received data is output on RPOS/RNEG (or RDATA in unipolar I/O mode).
2.1.1.2
T1 LOS Detection
During T1 operation, the ANSI T1.231 detection criterion is employed. The LXT336 asserts LOS if it receives 175 consecutive zeros, and de-asserts LOS when the signal reaches 12.5% ones density (i.e. 16 marks in a 128-bit window with no more than 99 consecutive zeros).
2.1.1.3
Data Recovery Mode LOS Detection
In data recovery mode, the LOS detector uses an analog detection scheme compliant with ITU-T G.775. Any signal 22 dB (typical) below the nominal 0 dB signal for more than approximately 16 s generates a LOS condition. LOS is cleared when the signal level of the first 1 rises to more than 21 dB (typical) below the minimum 0 dB level. During LOS conditions, received data is output on RPOS/RNEG.
2.1.1.4
In-Service Code Violation Monitoring
In unipolar AMI I/O Mode, the LXT336 reports bipolar violations using an active High output for one RCLK cycle on the BPV output. A bipolar violation, in AMI encoding mode, is two consecutive marks of the same polarity. With the HDB3 detector enabled (MODE pulled High), the decoder will detect AMI code violations that are not part of a zero substitution code. HDB3 code violations omit sequences of zeros that violate the coding rules. If an HDB3 code violation occurs, the decoder asserts the BPV output for one RCLK cycle during the period of the violating bit. In the event the decoder receives a sequence of four or more zeros, it asserts the BPV output during the entire sequence of violating data bits.
Datasheet
11
LXT336 -- Quad T1/E1 Receiver
3.0
Application Information
The LXT336 is well suited for both line interface equipment and monitoring applications. The following paragraphs describe the recommended configuration for these applications.
3.1
Monitoring Applications
Figure 3 shows a typical configuration for monitoring applications. The 432 resistors are usually included in the monitoring jack for DSX-1 applications. These resitors provide approximately 20dB of resistive attenuation when terminated into an 100 impedance. The 1:2 step up transformer in the receive interface is used to boost-up the signal as seen by the LXT336. The two resistors (Rx) determine the receive termination impedance and are selected according to the nominal cable impedance as specified in the table at the bottom of Figure 3. The series 1k resistors provide protection against surges coupled to the device. Due to the high input impedance of the LXT336, typically 40k , these series resistors do not affect receiver sensitivity.
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Datasheet
Quad T1/E1 Receiver -- LXT336
Figure 3. Typical Monitoring Application
TP TP
CROSS-CONNECT Reference Point
TP TP
TP
TP
TP
TP
432
W
432
W
432
W
432
W
1:2
Rx Rx 1:2 Rx Rx 1:2 Rx Rx 1:2 Rx Rx 1k 0.22F
LXT 336
RTIP1 RPOS1 RCLK1 RRING1 1k 1k 0.22F RRING2 1k 1k 0.22F RRING3 1k 1k 0.22F RRING4 1k RTIP4 RPOS4 RCLK4 RNEG4 RTIP3 RPOS3 RCLK3 RNEG3 RNEG2 RTIP2 RPOS2 RCLK2 RNEG1
es
Cable Impedance E1, 120 T1, 100
+5V VCC 33 F 0.1 F GND
3.1.1
Receive Line Interface Applications
Figure 4 shows the typical LXT336 configuration for receive line interface applications. A 1:1 transformer is used in combination with the appropriate termination resistors Rx. These resistors must be selected to match the line impedance as specified in the table at the bottom of Figure 4.
Datasheet
13
LXT336 -- Quad T1/E1 Receiver
Figure 4. Typical Receive Line Interface Application
1K Rx 0.22uF Rx RRING0 RNEG0 RCLK0
1:1
LXT 336
RTIP0 RPOS0
1:1
Rx
1K
RTIP1
RPOS1 RCLK1
0.22uF Rx RRING1 RTIP2
RNEG1 RPOS2 RCLK2
1:1
Rx
1K
0.22uF Rx RRING2
RNEG2
1:1
Rx
1K RTIP3 0.22uF Rx RRING3 1K +5V VCC 33 F 0.1 F RNEG3 MCLK GND 1.544/2.048 MHz RPOS3 RCLK3
Rx Values
Cable Impedance E1 75 37.5 E1 120 60 T1 100 50
Resistor values are 1%
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Datasheet
Quad T1/E1 Receiver -- LXT336
Table 2.
Transformer Specifications
Primary Inductance mH (min.) 1.2 Leakage Inductance H (max.) 0.60 Interwinding Capacitance pF (max.) 30 DCR (max.) 1.00 pri 1.20 sec Dielectric Breakdown Voltage V1 (min.) 1500 Vrms
Turns Ratio
1:2 or 1:1
1. This parameter is application dependent.
Datasheet
15
LXT336 -- Quad T1/E1 Receiver
4.0
Note:
Test Specifications
The minimum and maximum values in Table 3 through Table 9 and Figure 5 through Figure 7 represent the performance specifications of the LXT336 and are guaranteed by test except, where noted, by design or other correlation methods. Absolute Maximum Ratings
Sym RVCC, RGND
1
Table 3.
Parameter DC supply voltage Input voltage on any pin
Min -0.3 GND -0.3 -6 - -10 - -65 -
Max 6.0 RVCC + 0.3 RVCC + 0.3 100 10 20 +150 1
Unit V V V mA mA mA C W
VIN VIN
2
Input voltage on RTIP/RRING Transient latchup current on any pin Input current on any digital pin3 DC input current on RTIP, RRING Storage temperature Total package power dissipation
3
IIN IIN IIN TSTOR -
Caution: Exceeding these values may cause permanent damage to the device. Operation is not guaranteed under these conditions. Exposure to absolute maximum rating conditions for extended periods may adversely affect device reliability. 1. Referenced to ground. 2. Exceeding these values will cause SCR latch-up. 3. Constant input current.
Table 4.
Recommended Operating Conditions
Parameter Sym V+ TA Min 4.75 -40 Typ 5.0 25 Max 5.25 +85 Unit V
DC supply voltage Ambient operating temperature
C
Table 5.
DC Characteristics (Over Recommended Range)
Parameter High level input voltage Low level input voltage Sym VIH VIL
2
Min 2.0 -- 3.5 -- -10 -10
Typ1 - - - - -
Max - 0.8 - 0.4 +10 +10
Unit V V V V A A
Test Condition
Digital I/O pins High level output voltage Low level output voltage Input leakage current (digital input pins) Tristate leakage current
VOH VOL IIL IHZ
IOUT= -400A IOUT= 1.6 mA
2
pins 49 - 54, 59 - 64
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Output Drivers will output CMOS logic levels into CMOS loads. 3. Digital outputs driving a 50 pF load; all channels receiving line signal.
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Datasheet
Quad T1/E1 Receiver -- LXT336
Table 5.
DC Characteristics (Over Recommended Range) (Continued)
Parameter Low level input voltage High level input voltage Sym VINL VINH VINM IINL IINH PD PD ICCO Min - 3.5 2.3 - - - - - Typ1 - - 2.5 - - 250 200 - Max 1.5 - 2.7 50 50 340 290 10 Unit V V V A A mW mW mA pin 18 Test Condition
MODE input pin
Midrange input voltage Low level input current High level input current
Total power dissipation3 Power down current
E1 operation T1 operation
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Output Drivers will output CMOS logic levels into CMOS loads. 3. Digital outputs driving a 50 pF load; all channels receiving line signal.
Table 6.
E1 Receive Characteristics (Over Recommended Range)
Parameter Sym - DR S/I S/X SRE - - -
6
Min - 0.5 -15 -14 43 - - - 36 1.5 0.2 - - - -
Typ1 - - - - 50 2255 2.5 32 - - - 0.01 10 - 40
Max 12 4.2 - - 57 - - - - - - - - 0 -
Unit dB Vp dB dB % mV dB
Test Condition @1024 kHz
Permissible cable attenuation2 Receiver dynamic range Signal to noise interference margin 2, 6 Signal to single tone interference margin2 Data decision threshold Analog loss of signal threshold Loss of signal threshold hysteresis Consecutive zeros before loss of signal 1.2E-5 Hz to 20 Hz Low limit input jitter tolerance 3 RCLK output jitter4, 6 20 Hz to 2.4 kHz 8 kHz to 100 kHz 0 Hz to100 kHz
Per G.703, O.151, 6 dB of cable. O.151, 6 dB of cable Relative to peak input voltage.
G.775 recommendation U.I. U.I. U.I. U.I. kHz dB k @1024 kHz RTIP to RRING peak to peak G.823 recommendation
- - - - - - -
Clock recovery PLL 3 dB bandwidth PLL peaking
7
Receiver input impedance
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Line interface application. No errors shall occur when the combined signal attenuated by the maximum specified interconnecting cable loss is applied to the input port. See ITU O.151 recommendation for further details. 3. Sine wave jitter and wander with a peak to peak amplitude that corresponds at least to what is specified in Figure 6 shall not cause either a bit error or loss of frame alignment. As test signal an HDB3-coded digital signal with an electrical characteristic that complies with what is set forth in ITU G.703 shall be used. Test sequence is pseudo-random 215-1. See also ITU O.151. 4. If the LXT336 is configured as data receiver only and if a jitter free signal is applied to RTIP and RRING the added jitter must not exceed the specified value. 5. Equal to 22 dB below the nominal 0 dB level in 120 systems. 6. Guaranteed by design and other correlation methods. 7. Guaranteed by design and other correlation methods. There will be no jitter gain within the specified operating range.
Datasheet
17
LXT336 -- Quad T1/E1 Receiver
Table 6.
E1 Receive Characteristics (Over Recommended Range) (Continued)
Parameter 51 kHz-102 kHz Sym - - - Min 20 20 20 Typ1 - - - Max - - - Unit dB dB dB See Application Information section. Test Condition
Receiver return loss6
102-2048 kHz 2048 kHz-3072 kHz
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Line interface application. No errors shall occur when the combined signal attenuated by the maximum specified interconnecting cable loss is applied to the input port. See ITU O.151 recommendation for further details. 3. Sine wave jitter and wander with a peak to peak amplitude that corresponds at least to what is specified in Figure 6 shall not cause either a bit error or loss of frame alignment. As test signal an HDB3-coded digital signal with an electrical characteristic that complies with what is set forth in ITU G.703 shall be used. Test sequence is pseudo-random 215-1. See also ITU O.151. 4. If the LXT336 is configured as data receiver only and if a jitter free signal is applied to RTIP and RRING the added jitter must not exceed the specified value. 5. Equal to 22 dB below the nominal 0 dB level in 120 systems. 6. Guaranteed by design and other correlation methods. 7. Guaranteed by design and other correlation methods. There will be no jitter gain within the specified operating range.
Table 7.
T1 Receive Characteristics (Over Recommended Range)
Parameter Sym - DR US SRT - -
2
Min - 0.5 - 63 - - 10 0.3
Typ1 - - - 70 0.225 175 -
Max 12 4.2 62 77 - - -
Unit dB Vp % % V T1.231 U.I. U.I.
Test Condition @772 kHz, Line interface application
Permissible cable attenuation Receiver dynamic range Undershoot Data decision threshold Loss of signal threshold Allowable consecutive 0s before LOS Low limit input jitter tolerance 3 10 Hz to 192.9 Hz
Relative to peak input voltage.
-
6.43KHz to 40KHz - - - - - -
GR-499-CORE Category II equipment
Clock recovery PLL 3 dB bandwidth PLL peaking
4
- - - 20 20 20
10 - 40 - - -
- 0 - - - -
kHz dB k dB dB dB See Application Information section. RTIP to RRING @ 772 kHz
Receiver input impedance 51 kHz-102 kHz Input return loss2 102-2048 kHz 2048 kHz-3072 kHz
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Guaranteed by design and other correlation methods. 3. Sinewave jitter with a peak-to-peak amplitude that corresponds, at minimum, with Figure 7, shall not cause bit errors or loss of frame alignment. 4. Guaranteed by design and other correlation methods. There will be no jitter gain within the specified operating range.
18
Datasheet
Quad T1/E1 Receiver -- LXT336
Table 8.
Timing Characteristics (Over Recommended Range)
Parameter E1 Sym MCLK MCLK MCLKt -
5
Min - - - 40 - 40 447 594 203 270 - - 200 50 50 50 50 -
Typ1 2.048 1.544 50
Max - - - 60
Unit MHz MHz ppm % ppm % ns ns ns ns ns ns ns ns ns ns ns ns
Test Condition
Master clock frequency T1 Master clock tolerance Master clock duty cycle Receive clock capture range Receive clock duty cycle 2 Receive clock pulse width 2 Receive clock pulse width low time Receive clock pulse width high time RPOS/RNEG data low time (MCLK=High) RPOS/RNEG to RCLK rising setup time RCLK rising to RPOS/RNEG hold time E1 T1 E1 T1 E1 T1
3, 4
- RLCKd tPW tPW tPWL tPWL tPWH tPWH tPWD1 tSUR tSUR tHR tHR -
80 50 488 648 244 324 244 324 244 203 270 203 270 5
- 60 529 702 285 378 - - 300 - - - - -
From nominal
E1 T1 E1 T1
Delay time between RPOS/RNEG and RCLK
MCLK = High
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. RCLK duty cycle will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2 U.I. displacement for E1 and 0.4 U.I. for T1 operation). 3. This mode disables clock recovery. 4. If MCLK is High, the PLL clock recovery circuits are disabled. RPOSx and RNEGx are fed to an internal XOR gate that connects this output to RCLKx for external clock recovery. 5. Assuming a 50 ppm Master Clock (MCLK).
Figure 5. LXT336 Receive Timing Diagram
tPW
RCLK
tPWH
tPWL
tSUR
tHR
RPOS (CLKE=L) RNEG
tSUR tHR
RPOS (CLKE=H) RNEG
Datasheet
19
LXT336 -- Quad T1/E1 Receiver
Figure 6. E1 Jitter Tolerance--G.823
1000 UI
100 UI
Jitter
18 UI @ 1.7 Hz
LXT336 Jitter Tolerance (typical)
10 UI
3.0 UI @ 2 kHz
ITU G.823, Mar 1993 (E1)
1 UI
1.5 UI @ 20 Hz 1.5 UI @ 2.4 kHz 0.2 UI @ 18 kHz
0.8 UI 0.4 UI
.1 UI 1 Hz
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Frequency
20
Datasheet
Quad T1/E1 Receiver -- LXT336
Figure 7. T1 Jitter Tolerance--GR-499-CORE Category II
1000
100 Jitter Tolerance (UI)
LXT336 Jitter Tolerance (typical) GR-499-CORE Category II
10
1
10 UI @ 10 Hz
10 UI @ 192.9 Hz
0.3 UI @ 6.43 KHz
0.1 1 10 100 1000 10000 100000 Jitter Frequency (Hz)
Table 9.
Relevant Recommendations
Description
Recommendation
ITU
G.703 G.704 G.735 G.736 G.775 G.823 O.151 Physical/electrical characteristics of hierarchical digital interfaces Functional characteristics of interfaces associated with network nodes Characteristics of Primary PCM multiple equipment operating at 2048 kbit/s and offering digital access at 384 kbit/s and/or synchronous digital access at 64 kbit/s Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s Loss of signal (LOS) and alarm indication (AIS) defect detection and clearance criteria The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy Specification of instruments to measure error performance in digital systems
ANSI
T1.102 T1.231 Digital Hierarchy Electrical Interface Digital Hierarchy Layer 1 In-Service Digital Transmission Performance Monitoring
Bellcore
GR-499-CORE Transport Systems Generic Requirements
Datasheet
21
LXT336 -- Quad T1/E1 Receiver
5.0
Mechanical Specifications
Figure 8. Package Specifications
Quad Flat Pack
* Part Number: LXT336QE * 64-pin QFP * Extended Temperature Range -40C - +85C
D D1 D3
for sides with even number of pins
e
/2
3 E1 E3 E A L1 A2 1 A1 L B 3
Inches Dim Min A A1 A2 b D D1 D3 E E1 E3 e L L1 q3 q - 0.000 0.100 0.012 0.695 0.549 Max 0.130 0.010 0.120 0.018 0.715 0.553
Millimeters Min - 0.00 2.55 0.30 17.65 13.95 Max 3.30 0.25 3.05 0.45 18.15 14.05
0.472 REF. 0.695 0.549 0.715 0.553
12.00 REF. 17.65 13.95 18.15 14.05
0.472 REF. 0.031 BSC1 0.029 0.041
12.00 REF. 0.80 BSC1 0.73 1.03
0.077 REF. 5 0 16 7 5 0
1.95 REF. 16 7
1. BSC: Basic Spacing between Centers.
22
Datasheet

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